TRANSMISSION LINE MODEL OF A VLSI PACKAGE.

Academic Article

Abstract

  • For VLSI devices, it has become apparent that the package design can limit system performance. In order to describe more accurately the electrical interactions of devices within the system, a model of the package has been developed in which the lead runs are treated as transmission lines interfaced to lead runs on a PC board. A comparison has been made between the results obtained from the transmission line model and from a lumped parameter model of a VLSI package. A test line setup was used in the laboratory to validate the models.
  • Authors

    Published In

    Author List

  • Reed DJ; Shealy DL
  • Start Page

  • 127
  • End Page

  • 131
  • Volume

  • 26
  • Issue

  • 2