A fast programmable frequency divider with a wide dividing-ratio range and 50% duty-cycle

Academic Article

Abstract

  • A novel programmable frequency divider in 0.18-μm standard CMOS process is presented in this paper. With less cascode CMOS-stages, the proposed design achieves a higher operating frequency compared to that of the similar programmable frequency dividers reported in the literature. Test results demonstrate that the divider can operate up to 4.5GHz. Elimination of passive resistors in the proposed scheme provides an area efficient design approach. Design improvements to achieve 50% duty cycle are also presented. Due to the lower operating frequency of the 50% duty cycle correction unit, it only adds a very small amount- of power consumption penalty (∼ 10%) to the entire system. © IEICE 2007.
  • Authors

    Published In

    Digital Object Identifier (doi)

    Author List

  • Mo Z; Islam SK; Haider MR
  • Start Page

  • 672
  • End Page

  • 678
  • Volume

  • 4
  • Issue

  • 21