Hardware implementation of the Cube, Shuffle-Exchange, and Plus-Minus-2**i (PM2I) networks are examined. An analysis is made of recirculating (single stage) networks, multistage networks of combinational logic, and pipelined multistage networks. An expanded control structure for recirculating networks is introduced. It allows each processor to select its interconnection function independently of other processors. A multistage Shuffle-No Shuffle-Exchange network is presented. This network allows at each stage a Shuffle or no Shuffle followed by an Exchange. Finally, these networks are examined for their behavior in partitionable SIMD machines.